1. Field of Technology
The present invention relates to a receiving apparatus and receiving method for receiving signals transmitted using an OFDM (orthogonal frequency division multiplexing) system.
2. Description of Related Art
The OFDM signal transmission system modulates multiple mutually orthogonal carriers with the digital data being transmitted, and then multiplexes these modulated signals before transmission. Increasing the number of carriers from several hundred to several thousand for OFDM transmission significantly increases the symbol period compared with a single carrier system at the same transmission rate, and thus lowers the likelihood of multipath interference.
In a multipath environment, however, the amplitude and phase of each carrier changes on the channel, and the receiver must compensate for this change. All or part of an OFDM carrier is therefore used to transmit a pilot signal (a signal of known amplitude and phase).
The receiver can therefore estimate from the received pilot signal how the carrier changed on the channel, or more specifically can estimate the frequency response of the channel, and compensate accordingly. For example, the pilot signal used in the DVB-T (Digital Video Broadcast-Terrestrial: digital terrestrial television system used in Europe) and in the ISDB-T (Integrated Services Digital Broadcasting-Terrestrial: digital terrestrial television system used in Japan) is called a “scattered pilot” and is scattered over the carrier-symbol plane.
FIG. 11 is a block diagram of the OFDM signal demodulator 12a taught in U.S. Pat. No. 5,307,376 (Japanese Patent No. 3044899).
In the channel estimation circuit 23a shown in FIG. 11, the pilot signal extraction circuit 31 extracts the pilot signal contained in the output of the Fourier transform circuit 22, and outputs the result to the first input of a divider 33.
The pilot signal generator 32 generates a pilot signal of known amplitude and phase synchronized to the pilot signal extraction circuit 31, and outputs the resulting pilot signal to the second input of the divider 33.
The divider 33 then divides the output of the pilot signal extraction circuit 31 by the output of the pilot signal generator 32 to acquire the frequency response of the channel sampled at the pilot signal interval, and then outputs the result to the zero signal insertion circuit 34a. 
The zero signal insertion circuit 34a inserts a zero signal to the output of the divider 33, and supplies the result to the inverse Fourier transform circuit 35a. 
The inverse Fourier transform circuit 35a converts the frequency response output from the zero signal insertion circuit 34a to an impulse response, and outputs the result to the coring circuit 36a. 
The coring circuit 36a replaces data equal to or less than a specified threshold value in the output of the inverse Fourier transform circuit 35a with a zero signal, and outputs the result to the truncation circuit 37a. 
The truncation circuit 37a truncates the coring circuit output to a specified length and replaces other data with a zero signal to remove aliasing components (due to the frequency response, which is the input to the inverse Fourier transform circuit 35a, being sampled at the pilot signal period). The truncation circuit 37a outputs the result to the Fourier transform circuit 38a. 
The Fourier transform circuit 38a generates the interpolated frequency response (having values at positions other than the pilot signal) by Fourier transform of the impulse response output from the truncation circuit 37a. The output from the Fourier transform circuit 38a is then supplied as the output of the channel estimation circuit 23a to the second input to the divider 24.
Note that the DFT block 11 shown in FIG. 1 in the above-noted U.S. Pat. No. 5,307,376 corresponds to the Fourier transform circuit 22 shown in FIG. 11; the projection block 12 similarly shown in U.S. Pat. No. 5,307,376 corresponds to the divider 24 in FIG. 11; N/R sample extraction circuit 13 similarly shown in U.S. Pat. No. 5,307,376 corresponds to the circuit block including the pilot signal generator 32, divider 33, and zero signal insertion circuit 34a in FIG. 11; DFT−1 14 similarly shown in U.S. Pat. No. 5,307,376 corresponds to the inverse Fourier transform circuit 35a in FIG. 11; weighting circuit 15 similarly shown in U.S. Pat. No. 5,307,376 corresponds to the truncation circuit 37a in FIG. 11; DFT 16 similarly shown in U.S. Pat. No. 5,307,376 corresponds to the Fourier transform circuit 38a in FIG. 11; and thresholding block 17 similarly shown in U.S. Pat. No. 5,307,376 corresponds to the coring circuit 36a in FIG. 11.
Operation of the channel estimation circuit 23a shown in FIG. 11 is described next below with reference to FIG. 12. In FIG. 12 n is an index denoting the sampling time, and N denotes the number of samples processed by the inverse Fourier transform circuit 35a and Fourier transform circuit 38a. 
FIG. 12(a) shows an example of output from the inverse Fourier transform circuit 35a wherein 101a to 101d denote the normal impulse response, 102a to 102d through 112a to 112d denote the aliasing component, and the shaded area indicates the noise component 121. Aliasing occurs every N/12 samples because the scattered pilot signal in the DVB-T and ISDB-T systems is located every 12 carriers in each symbol.
FIG. 12(b) shows an example of output from the coring circuit 36a. The coring circuit 36a replaces data equal to or less than a specified threshold value (th) with zero signals. Data other than 101a to 101c, and 102a to 102c through 112a to 112c are therefore replaced by zero signals in the example shown in FIG. 12, and the power of noise components is therefore significantly suppressed.
FIG. 12(c) shows the output of the truncation circuit 37a. Note that aliasing components 102a to 102c through 112a to 112c are removed because the truncation circuit 37a substitutes zero signals for data with an index greater than N/12.
The frequency response acquired by the Fourier transform circuit 38a applying Fourier transform to the output of the truncation circuit 37a is thus not only interpolated, but estimation error due to noise is reduced by the operation of the coring circuit 36a. 
[Problem to be Solved]
When Impulse response does not coincide with the sampling time in this prior art configuration, output from the inverse Fourier transform circuit 35a has side lobes rather than being a single impulse. Furthermore, when impulse response is at the sampling time, output from the inverse Fourier transform circuit 35a also has side lobes rather than being a single impulse because the bandwidth of the output from the zero signal insertion circuit 34a is narrower than the input bandwidth of the inverse Fourier transform circuit 35a. 
When such impulse response is then input to the coring circuit 36a, side lobe components at or below the threshold value th are replaced by zero signals. This produces distortion in the frequency response obtained as the output of the Fourier transform circuit 38a. 
The inverse Fourier transform circuit 35a and Fourier transform circuit 38a must also process the same number of data samples as the main Fourier Transform circuit 22, leading to an increased circuit size if this operation is run in dedicated hardware, and an increased processing load if run in software using general-purpose hardware such as a DSP (digital signal processor).
The present invention is directed to solving the foregoing problem, and an object of the invention is to provide an OFDM signal receiving apparatus that reduces frequency response estimation error while also reducing the circuit scale required for a hardware implementation and the processing load required for a software implementation.